1. Field
Aspects of the present disclosure relate generally to scannable flop trays, and more particularly, to reducing the scan overhead of a scannable flop tray.
2. Background
Flip-flops may be used in a system to capture (latch) data values from one or more data signals for processing by various components of the system. The system may include scan circuitry to verify that the flip-flops are functioning correctly during testing. To do this, the scan circuitry receives a scan signal having a known test pattern, and scans the scan signal through the flip-flops. After the scan signal has been scanned through the flip-flops, the output scan signal is compared with an expected output scan signal to determine whether the flip-flops are functioning correctly. The expected output scan signal may be based on the known test pattern of the input scan signal and the expected functionality of the flip-flops. The scan circuitry adds overhead to the system due to the chip area and/power consumed by the scan circuitry.